1. Field of the Invention
The present invention relates to a silicon wafer made of a single crystal silicon ingot grown by the Czochralski method (hereinafter, referred to as CZ method) and a method for manufacturing the same wafer. And it relates more particularly to a silicon wafer to be used for manufacturing a semiconductor device such as an LSI and the like.
2. Description of the Related Art
A semiconductor device such as an LSI and the like needs to exhibit such excellent electric characteristics that a leakage current is a little in a pn junction and an MOS transistor has a high reliability in a gate oxide film. Crystal defects in a silicon wafer to be a substrate and contamination caused by a metal element in the wafer are mentioned as the causes deteriorating these characteristics.
Above all among metal elements in a single crystal silicon, an iron element is thought to have a bad influence and this iron element is taken in by contamination from an environment or an apparatus.
As a technique for capturing a metal element such as an iron element from an operating domain of a silicon wafer, an intrinsic gettering (IG) method and an extrinsic gettering (EG) method which make a wafer itself have a gettering ability to capture a metal element have been known up to now. And as a technique for removing metal from the surface of a wafer to be an operating domain, an RCA cleaning method which cleans a silicon wafer with an SC-1 solution composed of hydrogen peroxide and ammonium hydroxide and then cleans it with an SC-2 solution composed of hydrogen peroxide and dilute hydrochloric acid is known.
In case that a large amount of metal element is mixed into a single crystal silicon ingot grown by the CZ method, however, it is necessary to more and more complicate or advance a technique for removing or capturing the metal element from a silicon wafer.
On the other hand, in a process of manufacturing a semiconductor integrated circuit in recent years, existence of a microscopic defect of oxygen precipitation to be a nucleus of an oxidation induced stacking fault (hereinafter, referred to as OSF) or a crystal originated particle (hereinafter, referred to as COP) or an interstitial-type large dislocation (hereinafter referred to as L/D) is mentioned as a cause lowering the yield rate. The OSF is made by a fact that a microscopic defect to be the nucleus of a crystal is introduced when growing the crystal, is actualized in a thermal oxidation process and the like when manufacturing a semiconductor device, and causes a failure such as the increase of leakage current in a manufactured device. And when a mirror-polished silicon wafer is cleaned with a mixed solution of ammonia and hydrogen peroxide, pits are formed on the surface of the wafer and when the wafer is measured by a particle counter, these pits are detected as original particles. Said pit is caused by a crystal and is called a COP in order to distinguish it from an original particle. The COP being a pit on the surface of a wafer causes deterioration in electric characteristics such as time dependent dielectric breakdown (TDDB), time zero dielectric breakdown (TZDB) and the like of an oxide film. And existence of COPs on the surface of a wafer makes a step in a wiring process of a device and can cause breaking of wire. And it may cause leakage and the like in an isolation part of a device and reduces the yield rate of a product. Moreover, an L/D is called a dislocation cluster or also called a dislocation pit for the reason that a pit appears when a silicon wafer having this defect is immersed in a selective etching solution having hydrogen fluoride as the chief ingredient. The L/D also causes deterioration in electric characteristics such as leakage characteristic, isolation characteristic and the like, for example.
Due to the above-mentioned circumstances, it is necessary to reduce OSF, COP and L/D from a silicon wafer to be used for manufacturing a semiconductor integrated circuit.
A silicon wafer of no defect having no OSF, COP nor L/D is disclosed in Japanese Patent Laid-Open Publication No. Hei 11-1393. When assuming that a perfect domain in which there are no vacancy point defect agglomerates nor interstitial silicon point defect agglomerates in a single silicon crystal ingot is [P], this silicon wafer of no defect is a silicon wafer cut out from an ingot composed of a perfect domain [P]. A perfect domain [P] exists between a domain [I] in which interstitial silicon point defects exist dominantly and a domain [V] in which vacancy point defects exist dominantly in a single silicon crystal ingot. When assuming that the pulling speed of an ingot is V mm/minute and the temperature gradient at the interface between a molten silicon liquid and the ingot in the vertical direction is G ° C./mm, a silicon wafer composed of such a perfect domain [P] is made by determining the value of V/G mm2/(minute ° C.) so that OSFs to appear in the shape of a ring in a thermal oxidation process disappear in the center of the wafer.
On the other hand, it is required for a silicon wafer to have no OSF, COP nor L/D and further to be 1 to 15 Ωcm in resistivity so as to be compatible with an existing device process. And some of semiconductor device manufacturers demand a silicon wafer having the ability of gettering metal contamination generated in a device process. When a wafer having an insufficient gettering ability is contaminated by metal in a device process, a defective operation of a device is caused by a junction leakage or a trap state by a metal impurity and thereby the yield rate of the product is lowered.
A silicon wafer cut out from an ingot composed of said perfect domain [P] has ordinarily a resistivity of 1 to 15 Ωcm and does not have OSF, COP and L/D.
However, in a wafer being comparatively low in vacancy point defect density among silicon wafers composed of said perfect domain [P], oxygen precipitation does not always occur uniformly in the wafer in heat treatment in a device process and thereby the wafer sometimes cannot obtain a sufficient gettering effect.
And in case that the temperature gradient is constant, the value of V/G for producing a silicon wafer composed of a perfect domain [P] is in proportion to the pulling speed V of an ingot and it is required to pull the ingot at a comparatively low speed controlled within a narrow range, but it is not always technically easy to meet securely this requirement and the productivity of such an ingot also is not high.